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address generation in Chinese

Pronunciation:
How to pronounce "address generation""address generation" in a sentence"address generation" meaning

Translationmobile phoneMobile

  • 地址產(chǎn)生
  • 地址生成器

Examples

  • Agu address generation units
    地址生成單元
  • Agu address generation units
    地址產(chǎn)成單元
  • Adaptive stack cache with fast address generation policy can also avoid unnecessary memory traffic . stack cache can be disabled adaptively , when it is overflow
    該棧高速緩存在發(fā)生棧溢出時,能夠自適應(yīng)地關(guān)閉,以避免棧切換對處理器性能的影響。
  • The average ipc speedup is 5 . 9 % . 2 . adaptive stack cache with fast address generation policy is proposed by investigating stack access behavior of programs
    2 .通過對棧訪問行為的分析,提出一種棧高速緩存方案? ?快速地址計算的自適應(yīng)棧高速緩存組織方案。
  • Address generation for [ smtp ] has been enabled for all newly created recipients . do you want to automatically add this address type to all existing recipient e - mail addresses
    如果要為現(xiàn)有用戶生成此smtp地址，請單擊“是” 。否則，請單擊“否”以便僅向新創(chuàng)建的用戶提供此地址。
  • A split alu structure has been used to accomplish the simd operation and achieve high speed operation . in the rtl level design phase , we apply 3 methods to improve the speed of alu unit and dag ( data address generation unit ) which support the bit - reserve addressing and circular addressing : 1
    在dag模塊的設(shè)計中，以超前進(jìn)位加法器構(gòu)成進(jìn)位選擇結(jié)構(gòu)實(shí)現(xiàn)了對于比特反轉(zhuǎn)尋址計算，以兩級流水( id 、 da )實(shí)現(xiàn)了窗口尋址計算，滿足了時延要求。
  • These parameters include bandwidth , carrier frequency , signal duration and signal repeat frequency . according to the parameters , we select the method direct reading the stored digital waveform to realize the waveform generation in the third part , the waveform generator system control including communication control , timing control and address generation is designed
    第二部分研究了線性調(diào)頻信號參數(shù)間的內(nèi)在聯(lián)系，包括信號帶寬、中心頻率、持續(xù)時間及重復(fù)頻率等，設(shè)計了信號參數(shù)，并在前人研究的基礎(chǔ)上選擇了波形存儲直讀法作為信號產(chǎn)生方案。
  • Adaptive stack cache with fast address generation policy decouples stack references from other data references , improves instruction - level parallelism , reduces data cache pollution , and decreases data cache miss ratio . stack access latency can be reduced by using fast address generation scheme proposed here
    該方案將棧訪問從數(shù)據(jù)高速緩存的訪問中分離出來,充分利用?？臻g數(shù)據(jù)訪問的特點(diǎn),提高指令級并行度,減少數(shù)據(jù)高速緩存污染,降低數(shù)據(jù)高速緩存失效率,并采用快速地址計算策略,減少棧訪問的命中時間。

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